This application claims priority under 35 U.S.C. xc2xa7119 to Japan Application No. 2002-24195 and filed on Jan. 31, 2002, the entire content of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a reset control apparatus for controlling reset of electric/electronic devices, and particularly to a reset control apparatus for controlling rest of semiconductor integrated circuits.
2. Description of Related Art
Generally, electric/electronic devices such as semiconductor integrated circuits are brought into a reset state (initial state) when supplied with a reset signal (external reset signal) from the outside. The reset control apparatus is used to secure a reset period (internal reset period) to carry out the reset of the electric/electronic devices positively regardless of the input period (assertion period) of the external reset signal.
FIG. 6 is a block diagram showing a configuration of a conventional reset control apparatus. In FIG. 6, the reference numeral 1 designates an external reset terminal, 2 designates a noise canceler, 3 designates a D-type flip-flop, 4 designates a D-type flip-flop (F/F), 5 designates an AND gate, 6 designates a combinational circuit, 7 designates an AND gate, 8 designates a D-type latch, 9 designates a counter, 10 designates a D-type flip-flop (F/F), and 11 designates an inverter. The F/F 10 is supplied with a clock signal CLK, and the D-type latch 3 and F/F 4 are supplied with an inverted signal of the clock signal CLK, which is represented by a bar over the symbol CLK, and is called inverted clock signal CLK bar from now on. The conventional reset control apparatus produces the internal reset signal in response to the external reset signal supplied via the external reset terminal 1, and resets the semiconductor integrated circuit by the internal reset signal.
Next, the operation of the conventional reset control apparatus will be described.
FIG. 7 is a timing chart illustrating the operation of the reset control apparatus shown in FIG. 6. The reset operation will be described with reference to FIGS. 6 and 7.
First, it is assumed that the F/F 10 is supplied with the clock signal CLK, and the D-type latch 3 and F/F 4 are supplied with the inverted clock signal CLK bar as shown in FIG. 7. The external reset signal fed via the external reset terminal 1 is supplied to the D-type latch 3 through the noise canceler 2 as a noise canceled signal (NC signal) Here, the period in which the external reset signal is at a low level (L level) is referred to as an assertion period. The noise canceler 2 is used for eliminating noise superimposed on the external reset signal. Eliminating the noise by the noise canceler 2 can prevent the malfunction by noise,
The D-type latch 3 latches the NC signal by the inverted clock signal CLK bar, and outputs a latch signal. The latch signal is supplied to the F/F 4 that outputs an F/F signal. As shown in FIG. 6, the latch signal and F/F signal are supplied to the combinational circuit 6. When the external reset signal (the NC signal) is placed at the L level, and the inverted clock signal CLK bar changes from a high level (H level) to the L level, the Q terminal of the D-type latch 3 changes to the L level, that is, the latch signal becomes L level.
When the latch signal becomes L level, the F/F signal also becomes L level. When one of the latch signal and F/F signal becomes L level, the combinational circuit 6 delivers the internal reset signal. In other words, the internal reset signal becomes L level, thereby bringing about the internal reset input. In this way, the D-type latch 3 and F/F 4 synchronize the NC signal with the inverted clock signal CLK bar. In addition, the combinational circuit 6 outputs the internal reset signal in response to the NC signal.
The AND gate 5 is supplied with the latch signal and the inverted signal of the F/F signal. After the external reset signal (that is, the NC signal) changes from the L to H level, the D-type latch 3 places its Q terminal at the H level (that is, the latch signal is placed at the H level) at the timing at which the inverted clock signal CLK bar changes from L to H level. On the other hand, the F/F 4 brings the F/F signal to the H level one period of the inverted clock signal CLK bar has elapsed after the latch signal becomes H level. As a result, the AND gate 5 outputs a start (ST) signal of H level at the timing as illustrated in FIG. 7.
The ST signal is supplied to the AND gate 7 and D-type latch 8. The AND gate 7 is also supplied with the clock signal CLK. When both the clock signal CLK and ST signal are at H level, the AND gate 7 produces a signal (AND signal) of H level. As a result, the D-type latch 8 outputs an enabling (EN) signal which is placed at the H level when the AND-signal and ST signal are both at H level.
The EN signal is supplied to the combinational circuit 6 and counter 9. Receiving the EN signal of the H level, the combinational circuit 6 delivers the internal reset signal, that is, places the internal reset signal at the L level, even though the latch signal and F/F signal output from the D-type latch 3 and F/F 4 are at the H level.
On the other hand, the-counter 9, receiving the EN signal at the H level, starts counting of a predetermined time period (count enabled). When it counts the predetermined time period, the counter 9 counts up (overflows), and outputs an overflow (ovf) signal. The ovf signal is supplied to the F/F 10 that produces a clear signal in response to the ovf signal. In response to the clear signal, the D-type latch 8 is reset, and the EN signal is placed at the L level. In response to the EN signal placed at the L level, the combinational circuit 6 halts to deliver the internal reset-signal, that is, places the internal reset signal at the H level, thereby releasing the internal reset.
The NC signal is supplied to the counter 9 via the inverter 11 as the initialization signal, in response to which the counter 9 is initialized.
Thus generating the internal reset signal in response to the external reset signal enables the internal reset signal to positively reset internal resources of the semiconductor integrated circuit regardless of the assertion period of the external reset signal.
As described above, the conventional reset control apparatus must use the noise canceler to eliminate the noise superimposed on the external reset signal. Therefore, it is unavoidable that the external reset signal passing through the noise canceler, that is, the NC signal, has a shorter pulse width than the external reset signal. Thus, when the noise is superimposed on the external reset signal, the noise canceler reduces the pulse width of the external reset signal by an amount corresponding to the noise canceling width as shown in FIG. 8. As a result, the width of the NC signal becomes narrower than that of the external reset signal.
The conventional reset control apparatus samples the NC signal in synchronism with the clock signal, and generates the internal reset signal in response to the sampled result. Therefore, when the pulse width of the NC signal after the noise canceling is narrower than the period of the clock signal, the conventional reset control apparatus cannot sample the NC signal. As a result, the internal reset signal does not become L level as illustrated in FIG. 9, and the ST signal continues its L level. When the ST signal is at the L level, the EN signal also maintains the L level state, thereby preventing the counter from starting its count.
Thus, when the pulse width of the NC signal is narrower than the period of the clock signal, the conventional reset control apparatus cannot sample the NC signal, that is, cannot generate the internal reset signal. In other words, it cannot carry out the reset even if the external reset signal is input. This fact applies to the case where the pulse width of the external reset signal is narrower than the period of the clock signal when the external reset signal is supplied to the D-type latch 3 directly.
With the foregoing configuration, the conventional reset control apparatus cannot sample the NC signal if the pulse width of the external reset signal passing through the noise canceler (that is, the NC signal) is narrower than the period of the clock signal. As a result, it has a problem of being unable to generate the internal reset signal. Thus, it cannot perform the reset even though the external reset signal is input.
The conventional reset control apparatus generates the internal reset signal in response to the input of the external reset signal. Therefore, it generates the internal reset signal regardless of the state of the semiconductor integrated circuit whenever the external reset signal is supplied. For example, if the external reset signal is input while the CPU is carrying out the memory access in the semiconductor integrated circuit, the internal reset signal performs the reset. This presents a problem of destroying the contents of the memory. In other words, in spite of the operation to avoid the reset, it carries out the reset in response to the external reset signal, thereby offering a problem of causing a serious failure in the electric/electronic device such as a semiconductor integrated circuit.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a reset control apparatus capable of achieving the reset positively regardless of the pulse width of the external reset signal.
Another object of the present invention is to provide the reset control apparatus capable of carrying out the reset selectively depending on whether the reset avoiding operation is being performed or not.
According to a first aspect of the present invention, there is provided a reset control apparatus comprising: count start signal generating means for producing a count start signal in response to an external reset signal; counter means for starting counting in response to the count start signal; and reset signal generating means for outputting an internal reset signal in response to the external reset signal, and for halting the output of the internal reset signal when the counter means counts a predetermined count value. It offers an advantage of being able to reset without fail regardless of the pulse width of the external reset signal.
According to a second aspect of the present invention, there is provided a reset control apparatus comprising: count start signal generating means for producing a count start signal in response to the external reset signal; counter means for starting counting in response to the count start signal; first reset signal generating means for outputting a first internal reset signal in response to the external reset signal; and second reset signal generating means for outputting a second internal reset signal when the counter means counts a predetermined first count value. Using one of the first and second internal reset signals selectively, it offers an advantage of being able to carry out the reset selectively depending on whether the device to be reset is performing operation to avoid the reset or not.